1. Field of the Invention
The invention relates to memory circuits and more particularly to memory circuits utilizing variable threshold MNOS field effect transistors as memory elements.
2. Description of the Prior Art
Variable threshold field effect transistors are known in the art that may be utilized to form memory elements in computer memory arrays. Such a transistor is described in U.S. Pat. 3,590,337 entitled "Plural Dielectric Layered Electrically Alterable Non-Destructive Readout Memory Element", issued to H. A. R. Wegener on June 29, 1971 and assigned to the assignee of the present invention. Briefly, such transistors comprise source, drain and gate electrodes on a substrate and include a gate insulator that permits the conduction threshold of the transistor to be altered by the application of relatively large WRITE voltages between the gate electrode and the substrate. Binary valued thresholds may be established by the application of the WRITE voltages of opposite polarities respectively. The transistors are interrogated by applying a READ potential between the gate and substrate of a biased transistor, which READ potential is of a magnitude intermediate the established binary thresholds. The current drawn through the interrogated transistor is indicative of the established threshold and hence of the binary state of the element. Such memory readout is essentially non-destructive in that the application of the READ potential does not significantly alter the established threshold.
A variety of memory circuits have been devised utilizing the variable threshold transistors as memory cells, these circuits requiring various arrangements of READ and WRITE voltages and circuit configurations for performing these functions. The following U.S. Pat. Nos., which are assigned to the present assignee, exemplify such circuit arrangements: U.S. Pat. No. 3,508,211 entitled "Electrically Alterable Non-Destructive Readout Field Effect Transistor Memory", issued Apr. 21, 1970 to H. A. R. Wegener; U.S. Pat. No. 3,618,051 entitled "Non-Volative Read/Write Memory With Addressing" issued Nov. 2, 1971 to Robert E. Oleksiak; U.S. Pat. 3,691,535 entitled "Solid State Memory Array" issued Sept. 12, 1972 to Thomas R. Williams; and U.S. Pat. No. 3,747,072 entitled "Integrated Static MNOS Memory Circuit With Decoder" issued July 17, 1973 to Robert J. Lodi et al. Pending U.S. Pat. application Ser. No. 380,782, entitled "Integrated Variable Threshold MNOS Memory With Decoder and Operating Sequence", filed in the name of H. A. R. Wegener on July 19, 1973 and assigned to the assignee of the present invention, also describes such memory configurations.
In memory configurations such as those described in said U.S. Pat. Nos. 3,691,535; 3,618,051 and 3,747,072, it is often necessary to first set all of the memory cells to a predetermined state (which operation will hereinafter be designated as bulk clear) and then to switch selected memory transistors to the opposite state thereby establishing a desired data pattern for the memory. Preferably these memory arrays are fabricated as fully decoded, TTL logic compatible, monolithic circuit chips.
In order to perform the writing operations it is necessary to apply large magnitude positive and negative potentials between the gates and substrates of the memory transistors. A problem arises when utilizing a substrate such as an N type semi conductor on a P bulk material to form MOS P-channel transistors in that for one polarity of the large magnitude dual polarity voltages, the P-N junctions of the gate driving transistors for the memory array become forward biased thereby raising the entire substrate substantially to the level of the applied voltage. This action prevents the required large magnitude voltage from appearing between the gates and the substrates of the memory transistors.
A prior art solution to this problem has been to isolate the substrate of the memory transistors by an epitaxial layer and a diffused wall forming a PN-junction surrounding the memory array, as discussed in the aforesaid patents. Since the array of variable threshold memory transistors occupies a significant portion of the memory chip, the area required for isolation would necessarily be extensive. Isolation is effected by a reverse bias on the junction which in effect holds back the large magnitude voltages from the remainder of the chip thus permitting the above described clearing function to be performed. Such a large isolation junction adversely affects the manufacturing yield for such devices since when the junction area contains a defect (defects distributed over the area of the chip being unavoidable for reasonable manufacturing costs) voltage breakdown occurs across the isolation diffusion at the defect sites thereby causing rejection and discarding of the manufactured chip hence lowering the manufacturing yield and increasing the manufacturing costs.
One approach that may be utilized to avoid the extensive isolation diffusion would be to fabricate a plurality of additional conductors connected from a common terminal at the edge of the chip to the gate electrodes of all of the memory transistors respectively and to utilize the common terminals for the application of the appropriate polarity voltage. This approach is undesirable since it again significantly complicates the manufacturing procedures, hence markedly increasing manufacturing costs.
In addition to the above, these prior art memory arrangements utilize the word decoder and buffer inputs as well as the bit line terminals for the application of a plurality of precisely timed pulses to perform all of the necessary memory operations.
It is a primary object of the present invention to eliminate the necessity for extensive junction isolation and to include the capability of performing the bulk clear operation by the application of a single large magnitude pulse of a predetermined polarity to a single substrate terminal.